1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device, more specifically, it relates to a process for fabricating a bipolar integrated circuit (IC) which comprises bipolar transistors having a deep emitter region, to obtain a high withstand voltage, and elements having a shallow doped region in a semiconductor substrate. Such elements include a junction type field effect transistor (JFET), a shallow-emitter bipolar transistor, and a static induction transistor (SIT).
2. Description of the Prior Art
In known semiconductor devices, an operation amplifier and the like often comprises JFETs in a former stage and bipolar transistors in a latter stage. Heretofore, an IC for such an operation amplifier and the like has been fabricated by first forming bipolar transistors and then forming JFETs in a semiconductor bulk. The formation of the JFETs comprises at least one heat treatment for forming a channel region and a gate region in the channel region (typically, this treatment comprises a heat diffusion process or annealing after ion implantation). The temperatures used for these heat treatments are usually 800.degree. C. or higher, causing rediffusion of the doped impurity in an emitter region of the bipolar transistors.
In some cases, a bipolar transistor should have a deep emitter region, to obtain a high withstand voltage between the collector and emitter V.sub.CEO, of generally more than 10 volts, e.g., 30 volts or 40 volts, and a relatively rigid base width or a rigid difference in the depths of the base region and the emitter region, to obtain a sufficient current amplification factor h.sub.FE, such as 100. However, due to the above-mentioned rediffusion of the doped impurity in the emitter region, the base width, and therefore the current amplification factor h.sub.FE, are changed. In the former step of forming the bipolar transistors, the current amplification factor may be designed to become, for example, 40, and a current amplification factor H.sub.FE of, e.g., approximately 100, may be obtained after the heat treatment in the latter step of forming the JFETs. The precise control of the current amplification factor is, however, difficult in such a process.
Similar problems also occur in a process for fabricating an IC comprising a bipolar transistor having a high withstand voltage V.sub.CEO (a deep-emitter bipolar transistor) and a bipolar transistor having a shallow emitter region to obtain a high switching speed of the transistor (a shallow-emitter bipolar transistor), and in a process for fabricating an IC comprising a deep-emitter bipolar transistor and an SIT to obtain an excellent high-frequency characteristic, and the like. That is, the above-mentioned problems occur during a process for fabricating a semiconductor device which comprises a bipolar transistor having a deep emitter region and another element having a shallow doped region in the same semiconductor device, or substrate, the emitter region being substantially deeper than the shallow doped region, if the other element is formed after the bipolar transistor is formed, as is usual in a prior art process.